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sd-14590/91/92 synchro-to-digital converters description the sd-14590/91/92 series are high reliability synchro- or resolver-to-dig- ital converters with 14-bit-only, 16- bit-only, or 14- or 16-bit programma- ble resolution. this series of convert- ers feature high quality velocity out- put and hermetically sealed pack- ages. in addition, the sd-14591 and sd-14592 are pin-for-pin replace- ments for the natel 1024 and 1026, respectively. user-programmable resolution has been designed into the sd-14590 to increase the capabilities of modern motion control systems. the precise positioning attained at 16 bits of reso- lution and fast tracking of a 14-bit device are now available from one 36- pin double dip hybrid. velocity output (vel) from the sd-14590/91/92 is a v-based voltage of 0 to 3.5 vdc with a linearity to 2.0%. output voltage is positive for an increasing angle. the digital angle output from the sd- 14590/91/92 is a natural binary code, parallel positive logic and is ttl/cmos compatible. synchronization to a com- puter is accomplished via a converter busy (cb) and an inhibit (inh) input. applications because of its high reliability, accuracy, small size, and low power consumption, the sd-14590/91/92 is ideal for the most stringent and severe industrial and military ground or avionics applications. all models are available with mil-prf- 38534 processing as a standard option. designed with three-state output, the sd-14590/91/92 is especially well- suited for use with computer based systems. among the many possible applications are radar and navigation systems, fire control systems, flight instrumentation, and flight trainers or simulators. features ? replacement for natel?s 1024 and 1026 high quality velocity output eliminates tachometer accuracy to 1.3 arc minutes small size synchro or resolver input synthesized reference eliminates 180 lock-up s1 s2 s3 solid state synchro input option electronic scott t sin cos s1 s2 s3 solid state resolver input option resolver conditioner sin cos s4 direct input option voltage follower buffer sin cos sin cos input options v internal dc reference reference conditioner synthesized ref demod bit detect error processor high accuracy control transformer input option 16 bit ct transparent latch 16 bit output transparent latch 3 state ttl buffer 3 state ttl buffer 16 bit u-d counter edge triggered latch vco inhibit transparent latch power supply conditioner digital angle +5 v inh em bits 1-8 bits 9-14/16 el resolution control t 50 ns delay 0.4-1 s +10 v internal dc ref v (+5 v) +15v inh cb vel e bit +15 v unity gain buffer vel u t e d r u t gain e sin ( - ) 1 lsb antijitter feedback ref in rl rh sin cos q a gnd unity gain buffer (14590 only) ? 1996, 1999 data device corporation figure 1. sd-14590/91/92 block diagram
2 parameter unit value resolution (1) accuracy (2) repeatability differential linearity bits min lsb lsb 14, 16, 14 / 16 4, 2, or 1 +1 lsb 1 max 1 max in the 16th bit reference input characteristics carrier frequency ranges nominal 400 hz units nominal 60 hz units voltage range input impedance single ended differential common mode range hz hz vrms ohm ohm v 360-1000 47-1000 4-130 250k min 500k min 210 peak max 500 transient peak v ohm ohm v ohm ohm ohm v vrms ohm reference synthesizer sig/ref phase shift deg 45 typ, 60 max digital input/output logic type inputs inhibit (inh) enable msb ? s (em) (3) pull down enable lsb ? s (el) (3) pull down resolution control (a ) (sd-14590 only) (unused output data bits are set to 0) ttl/cmos compatible logic 0 = 0.8 v max logic 1 = 2.0 v min loading = 30 a max p.u. current source to +5 v//5 pf max cmos transient protected logic 0 inhibits data stable after 0.5 s logic 0 enables logic 1 high z 30a logic 0 enables logic 1 high z 30a 1 14 bits 0 16 bits table 1. sd-14590/91/92 specifications (contd) parameter unit value output parallel data converter busy (cb) bit drive capability bits 14 or 16 parallel lines; nat- ural binary angle, positive logic 0.4 to 2 s positive pulse; leading edge initiates counter update. logic 1 for fault. 50 pf plus rated logic drive. logic 0; 1 ttl load, 1.6 ma at 0.4 vmax logic 1; 10 ttl loads 0.4 ma at 2.8 v min high z; 10 a//5 pf max logic 0; 100 mv max driving cmos logic 1; +5 v supply minus 100 mv min driving cmos analog outputs velocity (vel) ac error (e) bias voltage (v) load mv rms kohm see tables 3 and 4 3.125 16 bit mode 6.130 14 bit mode 1/3 vs 10% 3 min dynamic characteristics see table 3. power supply characteristics nominal voltage voltage range max voltage w/o damage current % v ma max +15 v +5 v 510 +18 +8 25 10 temperature ranges operating -30x -10x storage c c c 0 to +70 -55 to +125 -65 to +150 physical characteristics size weight in. (mm) oz 1.9 x 0.78 x 0.21 (48.3 x 19.8 x 5.3) 36 pin double dip 0.7 max (20 g) transformers characteristics (see ordering information for list of transformers. reference transformers are optional for both solid-state and voltage follower input options.) 400 hz transformers reference transformer carrier frequency range voltage range input impedance breakdown voltage to gnd 360 - 1000 hz 18 - 130 v 40 k ? min 1200 v peak 11.8 v l-l 90 v l-l 17.5k 130k 11.5k 85k 11.8 v l-l 26 v l-l 23k 50k 46k 100k 23k 50k 25 max 60 max sin and cos resolver signals referenced to converter inter- nal dc reference v. 1 v nominal, 1.15 v max 15 v continuous 100 v peak transient zin > 20m//10 pf voltage follower table 1. sd-14590/91/92 specifications apply over temperature range, power supply range, reference, fre- quency and amplitude ranges; 10% signal amplitude variation; and up to 10% harmonic distortion in the reference. signal input characteristics (voltage options and minimum input impedance balanced) synchro zin line to line zin each line to gnd resolver zin single ended zin differential zin each line to gnd common mode range direct ( 1 v l-l ) input signal type sin/cos voltage range max voltage w/o damage input impedance
introduction the circuit shown in figure 1, the sd-14590/91/92 block dia- gram, consists of three main parts: the signal input; a feedback loop whose elements are the control transformer, demodulator, error processor, vco and up-down counter; and digital interface circuitry including various latches and buffers. signal inputs the sd-14590/91/92 series offer three input options: synchro, resolver, and direct. in a synchro or resolver mode, shaft angle data is transmitted as the ratio of carrier amplitudes across the input terminals. synchro signals, which are of the form sin cos t, sin( + 120 )cos t, and sin( + 240 )cos t are internally converted to resolver format; sin cos t and cos cos t. direct inputs accept 1 vrms inputs in resolver form, (sin cos t and cos cos t) and are buffered prior to conversion. figure 2 illus- trates synchro and resolver signals as a function of the angle . the solid-state signal and reference inputs are true differential inputs with high ac and dc common mode rejection. input impedance is maintained with power off. solid-state buffer input production: transient voltage suppression the solid-state signal and reference inputs are true differential inputs with high ac and dc common rejection so most applica- tions will not require units with isolation transformers. input impedance is maintained with power off. the current ac peak +dc common mode voltage should not exceed the values in table 1. 90 v line-to-line systems may have voltage transients which exceed the 500 v specification. these transients can destroy the thin-film input resistor network in the hybrid. therefore, 90 v l - l solid-state input modules may be protected by installing voltage suppressors as shown. voltage transients are likely to occur whenever synchro or resolver are switched on and off. for instance, a 1000 v transient can be generated when the prima- ry of a cx or tx driving a synchro or resolver input is opened. see figure 3. feedback loop the feedback loop produces a digital angle which tracks the analog input angle to within the specified accuracy of the con- 3 table1. sd-14590/91/92 specifications (contd) parameter unit value 360-1000 hz 700 v peak synchro z in (z so ) resolver z ln 180 ? 100k ? - 30k ? 20k ? 30k ? 47 - 440 hz 80 - 138 v rms; 115 v rms nominal resistive 600 k ? min resistive 500 v rms transformer isolated +r (in phase with rh-rl) and - r (in phase with rl- rh) derived from op-amps. short- circuit proof. 3.0 v nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. 47 - 440 hz 10 - 100 v rms l-l; 90 v rms l-l nominal 148 k ? min l-l balanced resistive 500 v rms transformer isolated resolver output: - sine (- s) + cosine (+c) derived from op-amps. short-circuit proof. 1.0 v rms nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. 30 90 150 210 270 330 360 (degrees) ccw in phase with rl-rh of converter and r2-r1 of cx. 0 s1-s3 = v sin max s3-s2 = v sin( + 120) max s2-s1 = v sin( + 240) max - v max + v max 30 90 150 210 270 330 360 (degrees) ccw in phase with rh-rl of converter and r2-r4 of rx. 0 s2-s4 = v cos max s1-s3 = v sin( ) max - v max + v max standard synchro control transmitter (cx) outputs as a function of ccw rotation from electrical zero (ez). figure 2. synchro and resolver signals standard resolver control transmitter (rx) outputs as a function of ccw rotation from electrical zero (ez) with r2-r4 excited. notes: (1) pin programmable for sd-14590 only; sd-14591 is 14 bits and sd-14592 is 16 bits. (2) see table 6. (3) see logic input/output section. transformers characteristics (cont ? d) signal transformer carrier frequency range breakdown voltage to gnd minimum input impedances (balanced) 90 v l-l 26 v l-l 11.8 v l-l 60 hz transformers reference transformer carrier frequency range input voltage range input impedance input common mode voltage output description output voltage power required signal transformer carrier frequency range input voltage range input impedance input common mode voltage output description output voltage power required
verter. the control transformer performs the following trigono- metric computation: sin( - ) = sin cos - cos sin where is the angle representing the resolver shaft position, and is the digital angle contained in the up/down counter. the track- ing process consists of continually adjusting to make ( - ) = 0, so that will represent the shaft position . the output of the demodulator is an analog dc level proportional to sin( - ). the error processor receives its input from the demodulator and inte- grates this sin( - ) error signal which then drives a voltage controlled oscillator (vco). the vco ? s clock pulses are accu- mulated by the up/down counter. the velocity voltage accuracy, linearity and offset are determined by the quality of the vco. functionally, the up/down counter is an incremental integrator. therefore, there are two stages of integration which make the converter a type ii tracking servo. in a type ii servo, the vco always settles to a counting rate which makes d /dt equal to d /dt without a lag. the output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. synthesized reference the synthesized reference section of the sd-14590 eliminates errors caused by quadrature voltage. due to the inductive nature of synchros and resolvers, their signals lead the reference signal (rh and rl) by about 6 . when an uncompensated reference signal is used to demodulate the control transformer ? s output, quadrature voltages are not completely eliminated. in a 14-bit converter it is not necessary to compensate for the reference signal ? s phase shift. a 6 phase shift will, however, cause prob- lems for the one minute accuracy converters. as shown in fig- ure 1, the converter synthesizes its own cos( t + ) reference signal from the sin cos( t + ), cos cos( t + ) signal inputs and from the cos t reference input. the phase angle of the syn- thesized reference is determined by the signal input. the refer- ence input is used to choose between the +180 and -180 phas- es. the synthesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be elim- inated. the synthesized reference circuit also eliminates the 180 false error null hangup. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. the magni- tude of this error is given by the following formula: error = quad/full scale (fs) signal * tan( ) where: error is in radians quad/fs signal is per unit quadrature input level. = signal to reference phase shift in degrees. a typical example of the magnitude of this source of error is as follows: quad/fs signal = .001 = 6 error = 0.35 min 1 lsb in the 16th bit. note: quad/fs is composed of static quadrature which is speci- fied by the resolver or synchro supplier plus the speed voltage which is given by: speed voltage = rotational speed/carrier frequency where: speed voltage is the per unit ratio of electrical rotational speed in rps divided by carrier frequency in hz. this error is totally negligible for 14-bit converters. for 16-bit con- verters where the highest accuracy possible is needed and where the quadrature and phase shift specifications can be high- er, this source of error could be significant. the reference syn- thesizer circuit in the converter which derives the reference from the input signal essentially sets to zero resulting in complete rejection of the quadrature. digital interface the digital interface circuitry has three main functions: to latch the output bits during an inhibit command so that the stable data can be read; to furnish both parallel and three-state data formats; and to act as a buffer between the internal cmos logic and the external ttl logic. in the sd-14590, applying an inhibit command will lock the data in the transparent latch without interfering with the continuous tracking of the feedback loop. therefore, the digital angle is always updated, and the inhibit can be applied for an arbitrary amount of time. the inhibit transparent latch and the 50 ns delay are part of the inhibit circuitry. the inhibit circuitry is described in detail in the logic input/output section. logic input/output logic angle outputs consist of 14 or 16 parallel data bits and converter busy (cb). all logic outputs are short-circuit proof to ground and +5 volts. the cb output is a positive, 0.4 to 2.0 s pulse. data changes about 50 ns after the leading edge of the pulse because of an internal delay. data is valid 0.2 s after the leading edge of cb, the angle is determined by the sum of the bits at logic ? 1. ? digital outputs are three-state and two bytes wide. for 14 bit only: 1-6 (msb ? s) are enabled by signal em, bits 7-14 (lsb ? s) are enabled by the signal el; for 14/16 program- 4 hybrid s3 s2 s1 rh rl cr1 cr2 s1 for 90 v synchro inputs 1n6071a cr3 s2 s3 hybrid s3 s2 s1 s4 for 90 v resolver inputs cr4 cr5 s3 s2 s1 s4 90 v l-l resolver input 1n6071a figure 3. connections for voltage transient suppressors cr4 and cr5 are 1n6068a, bipolar transient voltage suppressors or equivalent. cr1, cr2, and cr3 are 1n6068a, bipolar transient voltage suppressors or equivalent.
mable: 1-8 (msb ? s) are enabled by signal em, 9-14 (lsb ? s 14 bit) or 9-16 (lsb ? s 16 bit) are enabled by the signal el. outputs are valid (logic ? 1 ? or ? 0 ? ) 150 ns max after setting em or el low, and are high impedance within 100 ns max of setting em or el high. both em and el are internally pulled-down to +5 v at 30 a max. the inhibit (inh) input locks the transparent latch so the bits will remain stable while data is being transferred (see figure 1). the output is stable 0.5 s after inh is driven to logic ? 0, ? see fig- ure 4. a logic ? 0 ? at the t input latches the data, and a logic ? 1 ? applied to t will allow the bits to change. the inhibit transparent latch prevents the transmission of invalid data when there is an overlap between cb and inh. while the counter is not being updated, cb is at logic ? 0 ? and the inh latch is transparent. when cb goes to logic ? 1, ? the inh latch is locked. if cb occurs after inh has been applied, the latch will remain locked and its data will not change until cb returns to logic ? 0. ? if inh is applied during cb, the latch will not lock until the cb pulse is over. the purpose of the 50 ns delay is to prevent a race condition between cb and inh where the up-down counter begins to change as an inh is applied. whenever an input angle change occurs, the converter changes the digital angle in 1 lsb steps and gener- ates a converter busy pulse. output data change is initiated by the leading edge of the cb pulse, delayed by 50 ns, nominal. valid data is available at the outputs 0.2 s after the leading edge of cb, see figure 5. resolution control resolution control is via one logic input a. the sd-14590 (not the sd-14591 or sd-14592) has programmable resolution. built-in-test the built-ln-test output (bit) monitors the level of error (d) from the demodulator. d represents the difference in the input and output angles and ideally should be zero. if it exceeds approxi- mately 65 lsbs (of the selected resolution), the logic level at bit will change from a logic 0 to logic 1. this condition will occur dur- ing a large step and reset after the converter settles out. bit will also change to logic 1 for an over-velocity condition, because the converter loop cannot maintain input-output and/or if the con- verter malfunctions where it cannot maintain the loop at a null. bit will also be set if a total loss-of-signal (los) and/or a loss- of-reference (lor) occurs. dynamic performance a type ii servo loop (kv = ) and very high acceleration con- stants give the sd-14590 superior dynamic performance, as list- ed in table 3. if the power supply voltages are not the 15 vdc nominal values, the specified input rates will increase or decrease in proportion to the fractional change in voltage. a control loop block diagram is shown in figure 6, and an open loop bode plot is shown in figure 7. the values of the transfer function coefficients are shown in table 3. an inhibit input, regardless of its duration, does not affect the converter update. a simple method of interfacing to a computer asynchronously to cb is: (a) apply the inhibit, (b) wait 0.5 s minimum, (c) transfer the data and (d) release the inhibit. as long as the converter maximum tracking rate is not exceed- ed, there will be no lag in the converter output. if a step input 5 depends on d /dt 0.4-2.0 s cb 0.2 s data valid 6.1 s min figure 5. converter busy timing diagram data valid 0.5 s asynchronous to cb inh figure 4. inhibit timing diagram table 2. digital angle outputs bit deg/bit min/bit 1 msb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 10,800 5,400 2,700 1,350 675 387.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 note: em enables the msbs and el enables the lsbs. error processor input open loop transfer function = output where: 2 a = a a 1 2 velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 2 s a + 1 b 2 s s + 1 10b + - e a 2 s 2.75 figure 6. control loop block diagram
6 occurs, as when the power is initially applied, the response will be critically damped. figure 8 shows the response to a step input. after initial slewing at the maximum tracking rate of the convert- er, there is one overshoot (which is inherent in a type ii servo). the overshoot settling to final value is a function of the small sig- nal settling time. for velocity output, the simple filter shown in figure 9 will eliminate the one overshoot for step velocity input and will filter the carrier frequency ripple. analog outputs the analog outputs are velocity (vel) and ac error (e). both out- puts can swing 3.5 v min. with respect to v. the ac error, e, is proportional to the error ( - ) with a scaling of 6.310 mv/lsb (14-bit mode), and 3.125 mv/lsb (16-bit mode). velocity output characteristics are listed in table 4. velocity output the velocity output (vel) from the sd-14590 is a dc voltage proportional to angular velocity d /dt = d /dt. the velocity input is the second integrator, as shown in figure 6. its linearity is dependent solely on the linearity of the voltage controlled oscil- lator (vco). due to the highly linearized vel output, the electro- mechanical tachometer can now be eliminated from motion con- trol systems. bandwidth (bw) and the acceleration constant (ka) can be determined from the formula shown: bw(hz) = bw(rad/sec)/2 ka = a 2 outputs e and vel are not required for normal operation of the converter. v is used as an internal dc reference with the direct input option. maximum loading on v is 40k ohm; maximum load- ing for e and vel is 3k ohm. the velocity characteristics are shown in tables 4 and 5. output e is not closely controlled or characterized. consult the factory for further information. figures 10, 11, 12 are the synchro, resolver, and direct input connection diagrams respectively. output 91k vel (pin 23) 0.1 f rc = 1/a figure 9. velocity filter -12 db/oct 4 ba (bw) 2a -6 db/oct 10b (rad/sec) overshoot small signal settling time max slope equals tracking rate (slew rate) 2 1 settling time figure 8. response to a step input figure 7. open loop bode plot table 3. dynamic characteristics parameter units bandwidth 400 hz 60 hz resolution input frequency tracking rate bandwidth k a a1 a2 a b acc-1 lsb lag settling time bits hertz rps min hertz 1/sec 2 nom 1/sec nom 1/sec nom 1/sec nom 1/sec nom deg/sec 2 nom ms max 14 16 360-1000 10 2.5 54 * 12500 * 0.31 * 40k * 112 * 52 * 275k 69 300 800 note: * means the same as value to the left. table 4. velocity characteristics parameter units standard typ max polarity output voltage voltage scaling scale factor scale factor tc reversal error reversal error tc linearity linearity tc zero offset zero offset tc load v rps % ppm/ c % ppm/ c % output ppm/ c mv v/ c k ohm table 5. velocity voltage scaling bw resolution (values in rps/volt) 14 16 hl lo 2.8 0.71 0.71 0.17 note: if the resolution is changed while the input is changing, then the velocity output voltage and the digital output will have a transient until it settles to the new velocity scaling at a speed determined by the bandwidth. if additional information is required, consult the factory. 14 16 47-1000 2.5 0.61 14 * 780 * 0.078 * 10k * 28 * 13 * 17 4.3 1400 3400 positive for increasing angle. 3.5 see voltage scaling table 5. 10 15 100 200 12 25 50 12 25 50 15 35 25 50 - 3 min
7 reference oscillator parallel data rd-14590 stator rotor s3 s1 s2 s2 s1 s3 r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl s4 s4 el em reference oscillator parallel data xd-14590d4 stator rotor sin cos s2 s1 s3 r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl v s4 el em figure 10. synchro input connection diagram figure 12. direct input connection diagram reference oscillator parallel data sd-14590 stator rotor s3 s1 s2 s2 s1 s3 el em r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl figure 11. resolver input connection diagram
8 table 6. overall accuracy (min.) vs. resolution accuracy grade (minutes) resolution programmed to: 14 bit 16 bit 2.3 3.3 5.3 1.3 2.3 4.3 table 7. sd-14590/91/92 pin connection/functions pin no. function pin no. function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 s1(r) s1(s) - s2(r) s2(s) +c(x) s3(r) s3(s) +s(x) s4(r) - - 1 (msb) 2 3 4 5 6 7 8 9 10 11 12 13 14 (lsb-14 bit mode) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 note: 1. ? (r) ? means resolver, ? (s) ? means synchro, and ? (x) ? means direct. 2. * - no connection for 14-bit mode or sd-14591. nc nc (a for sd-14590) v inh +15 v ( vs) nc bit gnd +5 v (vl) e em el cb vel ( ) *16 (lsb-16 bit mode) *15 rl rh 1.900 max (48.26 max) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) 0.800 max (20.3 max) 0.600 0.005 (15.2 0.13) contrasting colored bead identifies pin 1 side view bottom view 0.25 min (6.35 min) 0.015 max (0.39) seating plane 36 19 1 18 1 18 19 36 .018.002 1.900 (max) .100 (typ) pin numbers are for ref. only 17 eq. sp. @ .100 = 1.700 (tol. noncum) 1 pin 1 denoted by contrasting colored bead or index mark .40 min (typ) .100.010 (typ) .010.002 (typ) .210 (max) .800 (max) top view side view notes: 1. dimensions are in inches. 2. metric equivalents are given for information only. 3. unless otherwise specified , tolerance is .005 inch (0.13mm). 4. lead identification numbers are for reference only. (consult factory for availability.) figure 14. sd-14590/91/92 mechanical outline 36-pin flat pack (ceramic) notes: 1. dimensions shown are in inches (millimeters). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.01(0.25) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements to mil-std-202e, method 208c 5. case is electrically floating. figure 13. sd-14590/91/92 mechanical outline 36-pin ddip (kovar) 1 +1 lsb 2 + 1 lsb 4 + 1 lsb
transformers figure 15 illustrates the transformer connection diagram. these transformers are designed for the voltage follower buffer input option to the sd-14590 (xd-14590 d4 or xd-14590 d5). however, the reference transformers may also be used with the solid-state buffer input options. passive transformers are considerably larger in size for 60 hz than for 400 hz. to minimize size, active transformers are utilized over passive devices for 60 hz. these active 60 hz transformers have op-amp outputs and require connection to a +15 v power supply. 9 1 3 5 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 xd-14590 d4 s c v 34 3 2 synchro input 1 3 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 s c v 3 2 resolver input s4 400 hz resolver transformer t1 21046 or 21047 or 21048 400 hz synchro transformer t1 21044 or 21045 s3 s2 s1 +15 -s -vs 24126 v s3 s2 s c v 34 3 2 synchro input 400 hz ref transformer 21049 60 hz synchro transformer 24126 s1 +15 v +c gnd t2 rh rh rl 20 19 ref input rl 10 6 +15 v rh rl v -r 24133 +r +15 gnd 19 20 ref input 60 hz ref transformer 24133 rh rl v rh rl 1 xd-14590 d4 5 xd-14590 d5 xd-14590 d4 xd-14590 d5 60 hz models 400 hz models 34 34 figure 15. transformer connection diagram
10 0.81 max (20.57) 0.30 max (7.62) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 123 5 109876 pin numbers for ref. only. dot on top face identifies pin 1. marking includes part number. terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass 21049 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) * s1 * s3 (+15 v) +15 v (-r) -s + * * (rh) s2 (rl) + * (v) v (+r) +c (-vs) -vs 24126 or (24133) 0.21 0.3 (5.33 0.76) 0.85 0.010 (21.59 0.25) 0.175 0.010 (4.45 0.25) noncumulative tolerance 0.040 0.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 0.03 (3.30 0.76) 1 5 6 10 reference input output to converter rh rl rh rl figure 16b. transformer mechanical outlines the mechanical outline is the same for the synchro input transformer (24126) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ) below. an asterisk (*) indicates that the pin is omitted. 400 hz reference transformer diagrams (t2) 2. schematic diagram 1. mechanical outline 60 hz synchro and reference transformer diagrams bottom views 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 1 345 109876 11 12 14 15 20 19 18 17 16 notes: 1. pin numbers are for reference only. 2. dot on top face identifies pins 1 and 11. 3. t1a and t1b pairing numbers listed in short side. 4. marking includes part number and t1a and t1b. terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 s4 figure 16a. 400 hz synchro and resolver transformer mechanical outlines and electrical schematics
11 ordering information xx-1459xxx-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection blank = none of the above accuracy: 2 = 5.2 minutes 4 = 2.6 minutes 5 = 1.3 minutes (16 bit only) process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c with variables test data 5 = -40 c to +85 c with variables test data 8 = 0 c to +70 c with variables test data input: 1 = 11.8/400 hz 2 = 90/400 hz 3 = 90/60 hz 4 = direct/400 hz 5 = direct/60 hz package: d = dip f = flat pack (consult factory for availability.) resolution: 0 = programmable (14 or 16 bits) 1 = 14 bit 2 = 16 bit input type: rd = resolver input sd = synchro input xd = direct input *standard ddc processing with burn-in and full temperature test ? see table below. ? 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing
12 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. c-10/00-0 printed in the u.s.a. type freq. ref. voltage l-l voltage ref. xfmr signal xfmr synchro synchro resolver resolver resolver synchro ? 400 hz 400 hz 400 hz 400 hz 400 hz 60 hz 115 v 26 v 115 v 26 v 26 v 115 v 90 v 11.8 v 90 v 26 v 11.8 v 90 v 21049 21049 21049 21049 21049 24133-1 24133-3 21045* 21044* 21048* 21047* 21046* 24126-1 24126-3 part numbers * the part number for each 400 hz synchro or resolver isolation transformer includes two separate modules as shown in the outline drawings. ? 60 hz synchro transformers are available in two temperature ranges: 1 = -55 c to +105 c 3 = 0 c to +70 c transformer ordering information reference and signal transformers for the voltage follower buffer input converters must be ordered separately from the followin g table: data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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